Module: Timer1/3 Module with Gate
Control
When using the Timer1 or Timer3 module, either
separately or simultaneously, a false overflow
event may occur after reloading the timer. The
event only occurs when the timer is configured for
Asynchronous Counter mode operation, and is
only problematic if the timer's interrupt is enabled.
During the Interrupt Service Routine (ISR), after
reloading the timer register (TMR1 and/or TMR3)
with a new value, the false overflow event can
occur upon the very next increment of the timer.
This sets the TMRx Overflow Interrupt Flag bit
(TMRxIF) and if the timer’s interrupts are enabled,
the interrupt service handler will again branch to
the interrupt vector on the next instruction clock,
after leaving the ISR. If interrupts are not enabled,
the TMRx Overflow Interrupt Flag bit will be set,
however, the firmware will not branch to the
interrupt vector.

Work around
While inside the Interrupt Service Routine (ISR),
create a loop routine that tests the timer for a
minimum increment of one count. Once the timer
has incremented by a minimum of one count, test
the Overflow Interrupt Flag bit (TMRxIF) and clear
it if set before leaving the ISR.