module add_acc #(
  parameter
    WI = 32,
    WO = 32
) (
  input clk,
  input reset,
  input [WI-1:0] in,
  output reg [WO-1:0] out
);

  always @(posedge clk)
    if (reset)
      out <= 0;
    else
      out <= out + in;

endmodule

module test;

  localparam
    WI = 8,
    WO = 8;

  reg clk;
  reg reset;

  reg [WI-1:0] data;
  wire [WO-1:0] acc;

  add_acc #(
    .WI (WI),
    .WO (WO)
  ) addacc0 (
    .clk (clk),
    .reset (reset),
    .in (data),
    .out (acc)
  );

  initial
    forever
      #5 clk <= ~clk;

  initial
    begin
      $monitor ("time: %6g   reset=%b data=%d acc=%d", $time, reset, data, acc);
      clk = 0;
      reset = 0;
      #10 reset = 1;

      #10 reset = 0;
      data = 128;
      #10 data = 64;
      #10 data = 32;
      #10 data = 16;
      #10 data = 8;
      #10 data = 4;
      #10 data = 2;
      #10 data = 1;
      #10 $finish;
    end

endmodule

module add_acc (
  input clk,
  input reset,
  input [31:0] in,
  output reg [31:0] out
);

  always @(posedge clk)
    if (reset)
      out <= 0;
    else
      out <= out + in;

endmodule