library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Rmeter

ENTITY Rmeter is
Port (
IN_PIN : in std_logic;
OUT_PIN : out std_logic
);
END Rmeter;

ARCHITECTURE STRUCTURE OF Rmeter IS

-- COMPONENTS

COMPONENT BUF
	PORT (
	IN0 : IN std_logic;
	Z : OUT std_logic
	); END COMPONENT;

-- GATE INSTANCES

BEGIN

INST1 : BUF	PORT MAP(
	IN0 => IN_PIN, 
	Z => OUT_PIN
);
END STRUCTURE;


-- Non inverting buffer

entity BUF is
    Port (
	 IN0: in std_logic;
	 Z: out std_logic
	 );
end BUF;

architecture BUF_Behavior of BUF is

begin

Z <= IN0;

end BUF_Behavior;